A comparison of SW/HW implementations of stream cipher encoders
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Data publikacji: 16.09.2014
Czasopismo Techniczne, 2013, Automatyka Zeszyt 3-AC (11) 2013, s. 83 - 92
https://doi.org/10.4467/2353737XCT.14.059.3967Autorzy
A comparison of SW/HW implementations of stream cipher encoders
In this paper, a new method of stream encoding and decoding is presented. It is developed on the basis of a derangement generator. Stream cipher D has been compared with other stream ciphers – E0, W7 and Phelix. Encoding and decoding algorithms have been implemented in C++ and VHDL programming languages. FPGA synthesis data has been reported for Spartan 3E and Virtex 4 devices from Xilinx. The hardware solution has been tested on the Digilent Nexys 2 500K board. Subsequently, comparative studies have been conducted for software and hardware coders, taking into account average coding time and average throughput for 16 input data files of different sizes. Conclusions resulting from the research are derived.
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Informacje: Czasopismo Techniczne, 2013, Automatyka Zeszyt 3-AC (11) 2013, s. 83 - 92
Typ artykułu: Oryginalny artykuł naukowy
Tytuły:
A comparison of SW/HW implementations of stream cipher encoders
A comparison of SW/HW implementations of stream cipher encoders
Katedra Automatyki i Technik Informacyjnych, Wydział Elektrotechniki i Inżynierii Komputerowej, Politechnika Krakowska; Katedra Komputerowych Systemów Automatyki, Instytut Technologii Komputerowych, Automatyki i Metrologii, Uniwersytet Narodowy „Lvivska Politechnika”
Faculty of Electrical and Computer Engineering, Cracow University of Technology
Publikacja: 16.09.2014
Status artykułu: Otwarte
Licencja: Żadna
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