TY - JOUR
TI - Java Based Transistor Level CPU Simulation Speedup Techniques
AU - Wojtowicz, Tomasz
TI - Java Based Transistor Level CPU Simulation Speedup Techniques
AB - Transistor level simulation of the CPU, while very accurate, brings also the performance challenge. MOS6502 CPU simulation algorithm is analysed with several optimisation techniques proposed. Application of these techniques improved the transistor level simulation speed by a factor of 3–4, bringing it to the levels on par with fastest RTL-level simulations so far.
VL - 2015
IS - Volume 24
PY - 2016
SN - 1732-3916
C1 - 2083-8476
SP - 179
EP - 195
DO - 10.4467/20838476SI.16.016.4357
UR - https://ejournals.eu/en/journal/schedae-informaticae/article/java-based-transistor-level-cpu-simulation-speedup-techniques
KW - CPU
KW - microarchitecture
KW - simulation
KW - registers
KW - pipeline
KW - activity
KW - 6502