Java Based Transistor Level CPU Simulation Speedup Techniques

Tomasz Wojtowicz

Titles

Abstract

Transistor level simulation of the CPU, while very accurate, brings also the performance challenge. MOS6502 CPU simulation algorithm is analysed with several optimisation techniques proposed. Application of these techniques improved the transistor level simulation speed by a factor of 3–4, bringing it to the levels on par with fastest RTL-level simulations so far.

Keywords

CPU, microarchitecture, simulation, registers, pipeline, activity, 6502

References

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Information

Information: Schedae Informaticae, 2015, Volume 24, pp. 179-195

DOI: https://doi.org/10.4467/20838476SI.16.016.4357

Article type: Original article

Titles:

Polish:

Java Based Transistor Level CPU Simulation Speedup Techniques

English:

Java Based Transistor Level CPU Simulation Speedup Techniques

Authors

Tomasz Wojtowicz

Department of Computer Sciences and Computer Methods, Pedagogical University

Published at: 11.04.2016

Article status: Open

Licence: None

Percentage share of authors:

Tomasz Wojtowicz (Author) - 100%

Article corrections:

-

Publication languages:

English

View count: 2120

Number of downloads: 2368

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