Java Based Transistor Level CPU Simulation Speedup Techniques
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RIS BIB ENDNOTEJava Based Transistor Level CPU Simulation Speedup Techniques
Publication date: 11.04.2016
Schedae Informaticae, 2015, Volume 24, pp. 179-195
https://doi.org/10.4467/20838476SI.16.016.4357Authors
Java Based Transistor Level CPU Simulation Speedup Techniques
Transistor level simulation of the CPU, while very accurate, brings also the performance challenge. MOS6502 CPU simulation algorithm is analysed with several optimisation techniques proposed. Application of these techniques improved the transistor level simulation speed by a factor of 3–4, bringing it to the levels on par with fastest RTL-level simulations so far.
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Information: Schedae Informaticae, 2015, Volume 24, pp. 179-195
Article type: Original article
Department of Computer Sciences and Computer Methods, Pedagogical University
Published at: 11.04.2016
Article status: Open
Licence: None
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EnglishView count: 2500
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