TY - JOUR
TI - Synthesis of 2-level combinatorial circuits with PKmin
AU - Kokosiński, Zbigniew
AU - Michalski, Tomasz
TI - Synthesis of 2-level combinatorial circuits with PKmin
AB - 
	In this paper a new design tool is presented that is useful in automated synthesis of combinatorial logic. PKmin program is devoted for synthesis of 2-level circuits composed of gates and PLAs, multi-level circuits and a functional decomposition of logical functions for LUT-based logic implementations in FPGA. It has been built on the basis of the research conducted at Cracow University of Technology. In the paper design algorithms implemented in PKmin are mutually compared. Then, an experimental efficiency comparison of gate and PLA-based 2-level synthesis with PKmin and Espresso design tools is reported.
VL - 2012
IS - Automatyka Zeszyt 1-AC (25) 2012
PY - 2012
SN - 0011-4561
C1 - 2353-737X
SP - 1
EP - 1
DO - 10.4467/2353737XCT.14.007.1784
UR - https://ejournals.eu/czasopismo/czasopismo-techniczne/artykul/synthesis-of-2-level-combinatorial-circuits-with-pkmin
KW - combinatorial logic
KW - PLD
KW - logical function minimization
KW - Kapralski algorithm
KW - Kazakov algorithm
KW - PKmin
KW - Espresso